1. Field of the Invention
The present invention relates to a buffer. More specifically, the present invention discloses a low voltage positive emitter coupled logic buffer in complimentary metal oxide silicon process.
2. Description of the Prior Art
Low-Voltage Positive Emitter Coupled Logic (LV-PECL) buffers are notorious for their difficult implementation in a complimentary metal oxide silicon (CMOS) process. Conventional PECL logic exactly matches the physical characteristics of Bipolar devices. However, the physical characteristics of MOSFET devices do not fit such PECL logic definition at all. Therefore, implementation of PECL logic in a CMOS process has traditionally been unsuccessful or at best unsatisfactory.
Additionally, with the evolution to lower voltage power supplies and lower voltage power requirements, design of such implementations has been further complicated.
Refer to FIG. 1A, which is a schematic illustrating a P-MOS amplifier with P-MOS switch of the prior art.
As shown in FIG. 1A, The—PMOS amplifier is embedded in a wide-band loop. In this configuration, the maximum switching frequency is limited to below 160 MHz in a 0.35 um process. This switching frequency is unacceptable for most applications.
Refer to FIG. 1B, which is a drawing illustrating the pull-up current of the circuit illustrated in FIG. 1A. In the circuit, the P-MOS switched current source delivers a pull-up current varying between two values. These two values are IupH and IupL.
A disadvantage of the conventional circuit is that the starting rise and fall times are both frequency and process dependent. Different buffers are needed to cover a plurality of output frequencies. Additionally, the maximum speed is limited to the switching capability of the P-MOSFET.
Therefore, there is need for a low voltage positive emitter coupled logic buffer that is realized in a CMOS process which provides high frequency switching capabilities.